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NTE9672 Integrated Circuit High Threshold Logic (HTL) Quad, 2-Input NAND Gate
Description: This NTE9672 is a Quad, 2-Input NAND gate with active output pull-up in a 14-Lead DIP style package. The active output arrangement allows the circuit to handle capacitive loads at a higher speed than is obtainable with a passive pullup configuration. Additionally, the impedance in the high state is considerably less, and consequently makes this device more immune to electrical noise. The active output configuration also allows for a more powerful arrangement to interface with discrete components. Electrical Characteristics: (TA = +25C unless otherwise specified)
Parameter Output Voltage Symbol VOL VOH Short-Circuit Current Reverse Current Output Leakage Current Forward Current Power Drain Current Total Device Switching Times ISC IR ICEX IF ICCL ICCH t1-3+ t1+3- IOL =12mA (Pulse In), IOH = -0.03mA (Pulse Out), VCC = 15V Test Conditions IOL = 12mA, VIH = 8.5V, VCCL = 14V IOH = -0.03mA, VIL = 6.5V, VCC = 15V, VCCL = 14V VCCH = 16V VR = 16V, VCCL = 14V VCEX = 16V VF = 1.5V, VR = 16V, VCCH = 16V VCCH = 16V Min - 12.5 -6.5 - - - - - - - Typ Max Unit - - - - - - - - - - 1.5 - -15 2 100 -1.2 6 20 200 100 V V mA A A mA mA mA ns ns
Logic Symbol 1 2 Input A1 4 5 9 10 12 13 6 Input B1 Output Y1 8 Input A2 Input B2 11 Output Y2 GND 3
Pin Connection Diagram
1 2 3 4 5 6 7
14 VCC 13 Input B4 12 Input A4 11 Output Y4 10 Input B3 9 8 Input A3 Output Y3
Positive Logic: 3 = 1 D 2 Input Loading Factor = 1 Output Loading Factor = 10 Propagation Delay Time = 110ns Typ Typical Total Power Dissipation Input High = 176mW Inputs Low = 52mW
14
8
1
7
.785 (19.95) Max
.300 (7.62)
.200 (5.08) Max
.100 (2.45) .600 (15.24)
.099 (2.5) Min

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